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bd7157a071
Signed-off-by: Luka Govedič <lgovedic@redhat.com> Signed-off-by: Luka Govedič <ProExpertProg@users.noreply.github.com>
267 lines
11 KiB
Plaintext
267 lines
11 KiB
Plaintext
/*
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* This file contains the CUDA kernels for the fused quantized layernorm.
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* The kernels correspond to the kernels in layernorm_kernels.cu, except they
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* also produce quantized output directly.
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* Currently, only static fp8 quantization is supported.
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*/
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#include "type_convert.cuh"
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#include "quantization/w8a8/fp8/common.cuh"
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#include "dispatch_utils.h"
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#include "cub_helpers.h"
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#include "core/batch_invariant.hpp"
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#include "quantization/vectorization_utils.cuh"
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#include <torch/cuda.h>
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#include <c10/cuda/CUDAGuard.h>
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namespace vllm {
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// TODO(woosuk): Further optimize this kernel.
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template <typename scalar_t, typename fp8_type>
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__global__ void rms_norm_static_fp8_quant_kernel(
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fp8_type* __restrict__ out, // [..., hidden_size]
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const scalar_t* __restrict__ input, // [..., hidden_size]
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const int input_stride,
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const scalar_t* __restrict__ weight, // [hidden_size]
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const float* __restrict__ scale, // [1]
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const float epsilon, const int num_tokens, const int hidden_size) {
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__shared__ float s_variance;
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float variance = 0.0f;
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const scalar_t* input_row = input + blockIdx.x * input_stride;
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constexpr int VEC_SIZE = 8;
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auto vec_op = [&variance](const vec_n_t<scalar_t, VEC_SIZE>& vec) {
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#pragma unroll
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for (int i = 0; i < VEC_SIZE; ++i) {
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float x = static_cast<float>(vec.val[i]);
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variance += x * x;
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}
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};
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auto scalar_op = [&variance](const scalar_t& val) {
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float x = static_cast<float>(val);
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variance += x * x;
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};
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vllm::vectorize_read_with_alignment<VEC_SIZE>(
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input_row, hidden_size, threadIdx.x, blockDim.x, vec_op, scalar_op);
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using BlockReduce = cub::BlockReduce<float, 1024>;
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__shared__ typename BlockReduce::TempStorage reduceStore;
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variance = BlockReduce(reduceStore).Reduce(variance, CubAddOp{}, blockDim.x);
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if (threadIdx.x == 0) {
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s_variance = rsqrtf(variance / hidden_size + epsilon);
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}
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__syncthreads();
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// invert scale to avoid division
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float const scale_inv = 1.0f / *scale;
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for (int idx = threadIdx.x; idx < hidden_size; idx += blockDim.x) {
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float x = (float)input[blockIdx.x * input_stride + idx];
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float const out_norm = ((scalar_t)(x * s_variance)) * weight[idx];
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out[blockIdx.x * hidden_size + idx] =
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scaled_fp8_conversion<true, fp8_type>(out_norm, scale_inv);
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}
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}
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/* Function specialization in the case of FP16/BF16 tensors.
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Additional optimizations we can make in this case are
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packed and vectorized operations, which help with the
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memory latency bottleneck. */
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template <typename scalar_t, int width, typename fp8_type>
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__global__ std::enable_if_t<(width > 0) && _typeConvert<scalar_t>::exists>
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fused_add_rms_norm_static_fp8_quant_kernel(
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fp8_type* __restrict__ out, // [..., hidden_size]
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scalar_t* __restrict__ input, // [..., hidden_size]
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const int input_stride,
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scalar_t* __restrict__ residual, // [..., hidden_size]
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const scalar_t* __restrict__ weight, // [hidden_size]
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const float* __restrict__ scale, // [1]
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const float epsilon, const int num_tokens, const int hidden_size) {
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// Sanity checks on our vector struct and type-punned pointer arithmetic
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static_assert(std::is_pod_v<_f16Vec<scalar_t, width>>);
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static_assert(sizeof(_f16Vec<scalar_t, width>) == sizeof(scalar_t) * width);
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const int vec_hidden_size = hidden_size / width;
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const int vec_input_stride = input_stride / width;
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__shared__ float s_variance;
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float variance = 0.0f;
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/* These and the argument pointers are all declared `restrict` as they are
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not aliased in practice. Argument pointers should not be dereferenced
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in this kernel as that would be undefined behavior */
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auto* __restrict__ input_v =
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reinterpret_cast<_f16Vec<scalar_t, width>*>(input);
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auto* __restrict__ residual_v =
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reinterpret_cast<_f16Vec<scalar_t, width>*>(residual);
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auto* __restrict__ weight_v =
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reinterpret_cast<const _f16Vec<scalar_t, width>*>(weight);
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for (int idx = threadIdx.x; idx < vec_hidden_size; idx += blockDim.x) {
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int stride_id = blockIdx.x * vec_input_stride + idx;
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int id = blockIdx.x * vec_hidden_size + idx;
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_f16Vec<scalar_t, width> temp = input_v[stride_id];
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temp += residual_v[id];
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variance += temp.sum_squares();
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residual_v[id] = temp;
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}
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using BlockReduce = cub::BlockReduce<float, 1024>;
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__shared__ typename BlockReduce::TempStorage reduceStore;
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variance = BlockReduce(reduceStore).Reduce(variance, CubAddOp{}, blockDim.x);
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if (threadIdx.x == 0) {
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s_variance = rsqrtf(variance / hidden_size + epsilon);
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}
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__syncthreads();
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// invert scale to avoid division
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float const scale_inv = 1.0f / *scale;
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for (int idx = threadIdx.x; idx < vec_hidden_size; idx += blockDim.x) {
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int id = blockIdx.x * vec_hidden_size + idx;
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_f16Vec<scalar_t, width> temp = residual_v[id];
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temp *= s_variance;
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temp *= weight_v[idx];
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#pragma unroll
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for (int i = 0; i < width; ++i) {
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out[id * width + i] =
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scaled_fp8_conversion<true, fp8_type>(float(temp.data[i]), scale_inv);
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}
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}
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}
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/* Generic fused_add_rms_norm_kernel
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The width field is not used here but necessary for other specializations.
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*/
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template <typename scalar_t, int width, typename fp8_type>
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__global__ std::enable_if_t<(width == 0) || !_typeConvert<scalar_t>::exists>
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fused_add_rms_norm_static_fp8_quant_kernel(
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fp8_type* __restrict__ out, // [..., hidden_size]
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scalar_t* __restrict__ input, // [..., hidden_size]
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const int input_stride,
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scalar_t* __restrict__ residual, // [..., hidden_size]
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const scalar_t* __restrict__ weight, // [hidden_size]
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const float* __restrict__ scale, // [1]
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const float epsilon, const int num_tokens, const int hidden_size) {
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__shared__ float s_variance;
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float variance = 0.0f;
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for (int idx = threadIdx.x; idx < hidden_size; idx += blockDim.x) {
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scalar_t z = input[blockIdx.x * input_stride + idx];
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z += residual[blockIdx.x * hidden_size + idx];
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float x = (float)z;
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variance += x * x;
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residual[blockIdx.x * hidden_size + idx] = z;
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}
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using BlockReduce = cub::BlockReduce<float, 1024>;
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__shared__ typename BlockReduce::TempStorage reduceStore;
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variance = BlockReduce(reduceStore).Reduce(variance, CubAddOp{}, blockDim.x);
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if (threadIdx.x == 0) {
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s_variance = rsqrtf(variance / hidden_size + epsilon);
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}
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__syncthreads();
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// invert scale to avoid division
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float const scale_inv = 1.0f / *scale;
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for (int idx = threadIdx.x; idx < hidden_size; idx += blockDim.x) {
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float x = (float)residual[blockIdx.x * hidden_size + idx];
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float const out_norm = ((scalar_t)(x * s_variance)) * weight[idx];
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out[blockIdx.x * hidden_size + idx] =
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scaled_fp8_conversion<true, fp8_type>(out_norm, scale_inv);
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}
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}
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} // namespace vllm
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void rms_norm_static_fp8_quant(torch::Tensor& out, // [..., hidden_size]
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torch::Tensor& input, // [..., hidden_size]
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torch::Tensor& weight, // [hidden_size]
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torch::Tensor& scale, // [1]
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double epsilon) {
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TORCH_CHECK(out.is_contiguous());
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int hidden_size = input.size(-1);
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int input_stride = input.stride(-2);
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int num_tokens = input.numel() / hidden_size;
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dim3 grid(num_tokens);
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dim3 block(std::min(hidden_size, 1024));
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
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VLLM_DISPATCH_FLOATING_TYPES(
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input.scalar_type(), "rms_norm_kernel_scalar_type", [&] {
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VLLM_DISPATCH_FP8_TYPES(
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out.scalar_type(), "rms_norm_kernel_fp8_type", [&] {
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vllm::rms_norm_static_fp8_quant_kernel<scalar_t, fp8_t>
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<<<grid, block, 0, stream>>>(
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out.data_ptr<fp8_t>(), input.data_ptr<scalar_t>(),
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input_stride, weight.data_ptr<scalar_t>(),
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scale.data_ptr<float>(), epsilon, num_tokens,
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hidden_size);
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});
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});
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}
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#define LAUNCH_FUSED_ADD_RMS_NORM(width) \
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VLLM_DISPATCH_FLOATING_TYPES( \
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input.scalar_type(), "fused_add_rms_norm_kernel_scalar_type", [&] { \
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VLLM_DISPATCH_FP8_TYPES( \
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out.scalar_type(), "fused_add_rms_norm_kernel_fp8_type", [&] { \
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vllm::fused_add_rms_norm_static_fp8_quant_kernel<scalar_t, \
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width, fp8_t> \
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<<<grid, block, 0, stream>>>( \
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out.data_ptr<fp8_t>(), input.data_ptr<scalar_t>(), \
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input_stride, residual.data_ptr<scalar_t>(), \
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weight.data_ptr<scalar_t>(), scale.data_ptr<float>(), \
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epsilon, num_tokens, hidden_size); \
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}); \
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});
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void fused_add_rms_norm_static_fp8_quant(
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torch::Tensor& out, // [..., hidden_size],
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torch::Tensor& input, // [..., hidden_size]
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torch::Tensor& residual, // [..., hidden_size]
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torch::Tensor& weight, // [hidden_size]
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torch::Tensor& scale, // [1]
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double epsilon) {
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TORCH_CHECK(out.is_contiguous());
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TORCH_CHECK(residual.is_contiguous());
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TORCH_CHECK(residual.scalar_type() == input.scalar_type());
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TORCH_CHECK(weight.scalar_type() == input.scalar_type());
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int hidden_size = input.size(-1);
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int input_stride = input.stride(-2);
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int num_tokens = input.numel() / hidden_size;
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dim3 grid(num_tokens);
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/* This kernel is memory-latency bound in many scenarios.
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When num_tokens is large, a smaller block size allows
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for increased block occupancy on CUs and better latency
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hiding on global mem ops. */
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const int max_block_size = (num_tokens < 256) ? 1024 : 256;
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dim3 block(std::min(hidden_size, max_block_size));
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
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/*If the tensor types are FP16/BF16, try to use the optimized kernel
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with packed + vectorized ops.
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Max optimization is achieved with a width-8 vector of FP16/BF16s
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since we can load at most 128 bits at once in a global memory op.
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However, this requires each tensor's data to be aligned to 16
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bytes.
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*/
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auto inp_ptr = reinterpret_cast<std::uintptr_t>(input.data_ptr());
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auto res_ptr = reinterpret_cast<std::uintptr_t>(residual.data_ptr());
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auto wt_ptr = reinterpret_cast<std::uintptr_t>(weight.data_ptr());
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bool ptrs_are_aligned =
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inp_ptr % 16 == 0 && res_ptr % 16 == 0 && wt_ptr % 16 == 0;
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bool batch_invariant_launch = vllm::vllm_is_batch_invariant();
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if (ptrs_are_aligned && hidden_size % 8 == 0 && input_stride % 8 == 0 &&
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!batch_invariant_launch) {
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LAUNCH_FUSED_ADD_RMS_NORM(8);
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} else {
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LAUNCH_FUSED_ADD_RMS_NORM(0);
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}
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}
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