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[Fix] Improve CPU backend compatibility for RISC-V (#25816)

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Signed-off-by: lyd1992 <liuyudong@iscas.ac.cn>
Signed-off-by: ihb2032 <1355790728@qq.com>
This commit is contained in:
ihb2032
2025-09-30 21:48:07 +08:00
committed by GitHub
parent bc546f76a1
commit bb6d43047e
1 changed files with 5 additions and 4 deletions
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9
vllm/engine/arg_utils.py
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@ -1160,11 +1160,12 @@ class EngineArgs:
# Set default arguments for V1 Engine.
self._set_default_args(usage_context, model_config)
# Disable chunked prefill for POWER (ppc64le)/ARM/s390x CPUs in V1
# Disable chunked prefill for POWER (ppc64le)/ARM/s390x/RISCV CPUs in V1
if current_platform.is_cpu() and current_platform.get_cpu_architecture(
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM):
logger.info("Chunked prefill is not supported for ARM and POWER "
"and S390X CPUs; "
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM,
CpuArchEnum.RISCV):
logger.info("Chunked prefill is not supported for ARM and POWER, "
"S390X and RISC-V CPUs; "
"disabling it for V1 backend.")
self.enable_chunked_prefill = False
assert self.enable_chunked_prefill is not None