mirror of
https://github.com/vllm-project/vllm-ascend.git
synced 2025-10-20 21:53:54 +08:00
### What this PR does / why we need it? - Adds the `mla_preprocess` custom kernel to provide an optimized pre-processing operator for Multi-head Latent Attention (MLA) on Ascend NPUs. - Wires the new kernel into the C++ extension pipeline so vLLM can invoke it directly, cutting Python-side tensor shuffling and memory copies that previously bottlenecked MLA compilation paths. ### Does this PR introduce any user-facing change? - No. The change only introduces a low-level kernel; public APIs and inference behavior remain unchanged. ### How was this patch tested? - Dedicated Ascend kernels are not covered by our CI yet, so no extra automated tests were added. Future MLA-focused regression runs will cover this path. - vLLM version: v0.11.0 Signed-off-by: Chen Chen <0109chenchen@gmail.com>
83 lines
4.5 KiB
C++
83 lines
4.5 KiB
C++
/* Adapted from
|
|
* https://gitee.com/ascend/ascend-transformer-boost.git
|
|
*
|
|
* Copyright (c) 2024 Huawei Technologies Co., Ltd.
|
|
* This file is a part of the CANN Open Software.
|
|
* Licensed under CANN Open Software License Agreement Version 1.0 (the "License").
|
|
* Please refer to the License for details. You may not use this file except in compliance with the License.
|
|
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
|
|
* INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
|
|
* See LICENSE in the root of the software repository for the full text of the License.
|
|
*/
|
|
#ifndef INCLUDE_MEM_H
|
|
#define INCLUDE_MEM_H
|
|
|
|
#include "hardware.h"
|
|
#include "kernel_event.h"
|
|
#include "kernel_tensor.h"
|
|
|
|
enum class BufferType { ASCEND_UB, ASCEND_CB, ASCEND_L0A, ASCEND_L0B, ASCEND_L0C, ASCEND_MAX };
|
|
|
|
template <BufferType BufferType_>
|
|
__aicore__ constexpr AscendC::TPosition GetPosition()
|
|
{
|
|
if constexpr (BufferType_ == BufferType::ASCEND_UB) {
|
|
return AscendC::TPosition::VECIN;
|
|
} else if constexpr (BufferType_ == BufferType::ASCEND_CB) {
|
|
return AscendC::TPosition::A1;
|
|
} else if constexpr (BufferType_ == BufferType::ASCEND_L0A) {
|
|
return AscendC::TPosition::A2;
|
|
} else if constexpr (BufferType_ == BufferType::ASCEND_L0B) {
|
|
return AscendC::TPosition::B2;
|
|
} else if constexpr (BufferType_ == BufferType::ASCEND_L0C) {
|
|
return AscendC::TPosition::CO1;
|
|
}
|
|
return AscendC::TPosition::GM;
|
|
}
|
|
|
|
template <ArchType ArchTag>
|
|
struct AsdopsBuffer {
|
|
public:
|
|
__aicore__ AsdopsBuffer()
|
|
{
|
|
constexpr uint32_t bufferSize[(uint32_t)BufferType::ASCEND_MAX] = {
|
|
HardwareInfo<ArchTag>::ubSize, HardwareInfo<ArchTag>::l1Size, HardwareInfo<ArchTag>::l0ASize,
|
|
HardwareInfo<ArchTag>::l0BSize, HardwareInfo<ArchTag>::l0CSize};
|
|
#ifdef __DAV_C220_VEC__
|
|
tensor[(uint32_t)BufferType::ASCEND_UB].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_UB]);
|
|
tensor[(uint32_t)BufferType::ASCEND_UB].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::VECIN);
|
|
#elif defined(__DAV_C220_CUBE__)
|
|
tensor[(uint32_t)BufferType::ASCEND_CB].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_CB]);
|
|
tensor[(uint32_t)BufferType::ASCEND_CB].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::A1);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0A].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0A]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0A].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::A2);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0B].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0B]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0B].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::B2);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0C].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0C]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0C].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::CO1);
|
|
#else
|
|
tensor[(uint32_t)BufferType::ASCEND_UB].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_UB]);
|
|
tensor[(uint32_t)BufferType::ASCEND_UB].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::VECIN);
|
|
tensor[(uint32_t)BufferType::ASCEND_CB].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_CB]);
|
|
tensor[(uint32_t)BufferType::ASCEND_CB].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::A1);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0A].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0A]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0A].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::A2);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0B].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0B]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0B].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::B2);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0C].InitBuffer(0, bufferSize[(uint32_t)BufferType::ASCEND_L0C]);
|
|
tensor[(uint32_t)BufferType::ASCEND_L0C].address_.logicPos = static_cast<uint8_t>(AscendC::TPosition::CO1);
|
|
#endif
|
|
};
|
|
|
|
template <BufferType BufferType_, typename DstDataType = half>
|
|
__aicore__ AscendC::LocalTensor<DstDataType> GetBuffer(const uint32_t offset) const
|
|
{
|
|
return tensor[(uint32_t)BufferType_][offset].template ReinterpretCast<DstDataType>();
|
|
}
|
|
|
|
public:
|
|
AscendC::LocalTensor<uint8_t> tensor[(uint32_t)BufferType::ASCEND_MAX];
|
|
};
|
|
|
|
#endif
|