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https://github.com/vllm-project/vllm-ascend.git
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579b7e5f21
### What this PR does / why we need it? Calculate in advance the workspace memory size needed for the PagedAttention operator to avoid deadlocks during resource cleanup. This PR requires torch_npu version 0920 or newer. ### How was this patch tested? - vLLM version: v0.11.0 --------- Signed-off-by: wangxiaoxin-sherie <wangxiaoxin7@huawei.com> Co-authored-by: wangxiaoxin-sherie <wangxiaoxin7@huawei.com>
104 lines
4.6 KiB
Python
104 lines
4.6 KiB
Python
#
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# Copyright (c) 2025 Huawei Technologies Co., Ltd. All Rights Reserved.
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# Copyright 2023 The vLLM team.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# This file is a part of the vllm-ascend project.
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# Adapted from vllm/tests/basic_correctness/test_basic_correctness.py
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#
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"""Compare the short outputs of HF and vLLM when using greedy sampling.
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Run `pytest tests/e2e/multicard/test_qwen3_moe.py`.
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"""
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import os
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from vllm import SamplingParams
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from tests.e2e.conftest import VllmRunner
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from tests.e2e.model_utils import check_outputs_equal
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def test_models_distributed_Qwen3_MOE_TP2_WITH_FULLGRAPH():
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if 'HCCL_OP_EXPANSION_MODE' in os.environ:
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del os.environ['HCCL_OP_EXPANSION_MODE']
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prompts = [
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('Solve the following math problem step by step.'
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'The last line of your response should be of the form Answer: '
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'$Answer (without quotes) where $Answer is the answer to the problem.\n\n'
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'In triangle $ABC$, $\\sin \\angle A = \\frac{4}{5}$ and $\\angle A < 90^\\circ$. Let $D$'
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'be a point outside triangle $ABC$ such that $\\angle BAD = \\angle DAC$,'
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'$\\angle BDC = 90^\\circ$. Suppose $AD = 1$ and $\\frac{BD}{CD} = \\frac{3}{2}$.'
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'If $AB + AC$ can be expressed in the form $\\frac{a\\sqrt{b}}{c}$,'
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'where $a, b, c$ are pairwise relatively prime integers, find $a + b + c$.'
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),
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('Solve the following math problem step by step.'
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'The last line of your response should be of the form Answer: '
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'$Answer (without quotes) where $Answer is the answer to the problem.\n\n'
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'Let $ABCD$ be a unit square in the plane. Points $X$ and $Y$ are chosen'
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'independently and uniformly at random on the perimeter of $ABCD$.'
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'If the expected value of the area of triangle $\\triangle AXY$'
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'can be expressed as $\\frac{m}{n}$, for relatively prime positive'
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'integers $m$ and $n$, compute $m+n$.'),
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('Solve the following math problem step by step.'
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'The last line of your response should be of the form Answer: '
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'$Answer (without quotes) where $Answer is the answer to the problem.\n\n'
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'Let $a, b, c$ be distinct numbers such that the equations $x^2 + ax + 1 = 0$'
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'and $x^2 + bx + c = 0$ have a common real root, and the equations $x^2 + x + a = 0$'
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'and $x^2 + cx + b = 0$ also have a common real root.'
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'Compute the sum $a + b + c$.')
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]
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model = "Qwen/Qwen3-30B-A3B"
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sampling_params = SamplingParams(max_tokens=5,
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n=1,
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temperature=0.0,
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top_p=1.0,
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top_k=1)
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with VllmRunner(model,
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max_model_len=1024,
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tensor_parallel_size=2,
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enforce_eager=False,
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gpu_memory_utilization=0.95,
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compilation_config={
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"cudagraph_capture_sizes":
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[4, 8, 12, 16, 24, 32, 40, 48],
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"cudagraph_mode": "FULL_DECODE_ONLY"
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}) as runner:
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vllm_fullgraph_outputs = runner.model.generate(prompts,
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sampling_params)
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with VllmRunner(
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model,
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max_model_len=1024,
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tensor_parallel_size=2,
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enforce_eager=True,
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gpu_memory_utilization=0.95,
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) as runner:
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vllm_eager_outputs = runner.model.generate(prompts, sampling_params)
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vllm_fullgraph_outputs_list = []
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for output in vllm_fullgraph_outputs:
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vllm_fullgraph_outputs_list.append(
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(output.outputs[0].index, output.outputs[0].text))
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vllm_eager_outputs_list = []
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for output in vllm_eager_outputs:
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vllm_eager_outputs_list.append(
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(output.outputs[0].index, output.outputs[0].text))
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check_outputs_equal(
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outputs_0_lst=vllm_eager_outputs_list,
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outputs_1_lst=vllm_fullgraph_outputs_list,
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name_0="vllm_eager_outputs",
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name_1="vllm_fullgraph_outputs",
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)
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