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54db14e390
Summary: The goal of this PR is to add an infrastructure; to convert(hipify) CUDA ops into [HIP](https://github.com/ROCm-Developer-Tools/HIP) ops , at **compile** time. Note that HIP ops, which are portable c++ code, can run on AMD and NVIDIA platform. Pull Request resolved: https://github.com/pytorch/pytorch/pull/9322 Differential Revision: D8884707 Pulled By: bddppq fbshipit-source-id: dabc6319546002c308c10528238e6684f7aef0f8
47 lines
1.1 KiB
C++
47 lines
1.1 KiB
C++
#pragma once
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#include <cfloat>
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#include "caffe2/core/context.h"
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#include "caffe2/core/context_gpu.h"
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#include "caffe2/core/logging.h"
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#include "caffe2/core/operator.h"
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#include "caffe2/operators/conv_pool_op_base.h"
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#include "caffe2/operators/pool_op.h"
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#include "caffe2/utils/math.h"
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namespace caffe2 {
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class MaxPoolWithIndexOp final : public ConvPoolOpBase<CUDAContext> {
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public:
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USE_CONV_POOL_BASE_FUNCTIONS(CUDAContext);
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MaxPoolWithIndexOp(const OperatorDef& operator_def, Workspace* ws)
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: ConvPoolOpBase<CUDAContext>(operator_def, ws) {}
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~MaxPoolWithIndexOp() {}
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template <typename T>
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bool DoRunWithType();
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bool RunOnDevice() override;
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// Input: X
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// Output: Y, mask
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};
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class MaxPoolWithIndexGradientOp final : public ConvPoolOpBase<CUDAContext> {
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public:
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USE_CONV_POOL_BASE_FUNCTIONS(CUDAContext);
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MaxPoolWithIndexGradientOp(const OperatorDef& operator_def, Workspace* ws)
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: ConvPoolOpBase<CUDAContext>(operator_def, ws) {}
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~MaxPoolWithIndexGradientOp() {}
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template <typename T>
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bool DoRunWithType();
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bool RunOnDevice() override;
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// Input: X, dY, mask
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// Output: dX
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};
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}; // namespace caffe2
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