mirror of
https://github.com/pytorch/pytorch.git
synced 2025-10-20 12:54:11 +08:00
Enable more C++ warnings (#143355)
Fixes #ISSUE_NUMBER Pull Request resolved: https://github.com/pytorch/pytorch/pull/143355 Approved by: https://github.com/albanD
This commit is contained in:
@ -106,6 +106,8 @@ StatementMacros:
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- C10_DEFINE_int32
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- C10_DEFINE_int64
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- C10_DEFINE_string
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- C10_DEFINE_REGISTRY_WITHOUT_WARNING
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- C10_REGISTER_CREATOR
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- DEFINE_BINARY
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- PyObject_HEAD
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- PyObject_VAR_HEAD
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@ -1057,7 +1057,6 @@ if(NOT MSVC)
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append_cxx_flag_if_supported("-Wconstant-conversion" CMAKE_CXX_FLAGS)
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append_cxx_flag_if_supported("-Wno-aligned-allocation-unavailable"
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CMAKE_CXX_FLAGS)
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append_cxx_flag_if_supported("-Wno-missing-braces" CMAKE_CXX_FLAGS)
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append_cxx_flag_if_supported("-Qunused-arguments" CMAKE_CXX_FLAGS)
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if(${USE_COLORIZE_OUTPUT})
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@ -1,5 +1,4 @@
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#define TORCH_ASSERT_ONLY_METHOD_OPERATORS
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#include <vector>
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#include <ATen/core/Tensor.h>
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#include <ATen/Parallel.h>
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@ -116,7 +115,7 @@ Tensor fbgemm_linear_int8_weight_fp32_activation(
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const Tensor bias_contig = bias.contiguous();
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// Allocate output Tensor and a buffer for fbgemmPacked to use
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std::vector<int64_t> output_size = input.sizes().vec();
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auto output_size = input.sizes().vec();
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output_size.back() = N;
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Tensor output = at::empty(output_size, input.options().dtype(at::kFloat), LEGACY_CONTIGUOUS_MEMORY_FORMAT);
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Tensor buffer = at::empty(output_size, input.options().dtype(at::kInt), LEGACY_CONTIGUOUS_MEMORY_FORMAT);
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@ -62,8 +62,6 @@
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#include <utility>
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#endif
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int register_linear_params();
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namespace at::native {
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namespace {
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@ -19,8 +19,6 @@
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#include <ATen/ops/from_blob.h>
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#endif
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int register_linear_params();
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#ifdef USE_FBGEMM
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std::tuple<at::Tensor, std::optional<at::Tensor>> PackedLinearWeight::unpack() {
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auto packB = w.get();
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@ -28,7 +28,6 @@
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#include <utility>
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#endif
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int register_embedding_params();
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#ifdef USE_FBGEMM
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@ -381,9 +380,7 @@ namespace {
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}
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}
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template <int kSpatialDim = 2>
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TORCH_API int
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register_conv_params() {
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template <int kSpatialDim> int register_conv_params() {
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static auto register_conv_params =
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torch::selective_class_<ConvPackedParamsBase<kSpatialDim>>(
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"quantized", TORCH_SELECTIVE_CLASS(_hack_int_to_class_name(kSpatialDim)))
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@ -420,9 +417,7 @@ TORCH_API int register_conv_params<2>();
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template
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TORCH_API int register_conv_params<3>();
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TORCH_API int register_linear_params();
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TORCH_API int register_linear_params() {
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int register_linear_params() {
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using SerializationType = std::tuple<at::Tensor, std::optional<at::Tensor>>;
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static auto register_linear_params =
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torch::selective_class_<LinearPackedParamsBase>(
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@ -6,7 +6,7 @@
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#include <c10/core/QScheme.h>
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#include <c10/util/irange.h>
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#ifdef USE_FBGEMM
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#if defined(USE_FBGEMM) && __has_include(<fbgemm/Fbgemm.h>)
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#include <fbgemm/Fbgemm.h>
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C10_DIAGNOSTIC_PUSH_AND_IGNORED_IF_DEFINED("-Winconsistent-missing-destructor-override")
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#include <fbgemm/FbgemmFP16.h>
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@ -407,3 +407,8 @@ struct TORCH_API PackedEmbeddingBagWeight : public EmbeddingPackedParamsBase {
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bool include_last_offset,
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bool is_embedding_op) override;
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};
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TORCH_API int register_linear_params();
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int register_embedding_params();
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template <int kSpatialDim = 2> TORCH_API int register_conv_params();
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@ -31,8 +31,6 @@
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#include <algorithm>
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#include <string>
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int register_linear_params();
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#ifdef USE_FBGEMM
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template <bool ReluFused>
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at::Tensor& PackedLinearWeight::apply_impl(
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@ -29,8 +29,6 @@
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#include <string>
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#include <type_traits>
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int register_linear_params();
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#ifdef USE_FBGEMM
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template <bool ReluFused>
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at::Tensor PackedLinearWeight::apply_dynamic_impl(
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@ -31,8 +31,6 @@
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#include <utility>
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#include <vector>
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int register_linear_params();
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#ifdef USE_FBGEMM
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namespace {
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// Calculate the column offsets.
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@ -9,6 +9,7 @@
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#include <ATen/cuda/Exceptions.h>
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#include <ATen/cudnn/Handle.h>
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#include <ATen/native/cudnn/ConvShared.h>
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#include <ATen/native/quantized/cpu/fbgemm_utils.h>
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#include <ATen/native/quantized/cudnn/utils.h>
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#include <ATen/native/quantized/ConvUtils.h>
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#include <ATen/native/quantized/PackedParams.h>
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@ -22,12 +23,6 @@
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#include <unordered_map>
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#include <vector>
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template <int kSpatialDim = 2>
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int register_conv_params();
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extern template int register_conv_params<2>();
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extern template int register_conv_params<3>();
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// TODO: there is a table from input dtype and weight dtype to operator qdtype,
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// we can derive the operator dtype based on input dtype
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cudnn_frontend::ConvDesc_v8 getConvDescriptor(cudnnDataType_t dataType, c10::IntArrayRef padding, c10::IntArrayRef stride, c10::IntArrayRef dilation) {
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@ -5,6 +5,7 @@
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#include <ATen/ATen.h>
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#include <torch/library.h>
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#include <ATen/native/quantized/cpu/fbgemm_utils.h>
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#include <ATen/native/quantized/cpu/QuantUtils.h>
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#include <ATen/native/quantized/cudnn/utils.h>
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#include <ATen/native/quantized/PackedParams.h>
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@ -15,12 +16,6 @@
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#include <utility>
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template <int kSpatialDim = 2>
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int register_conv_params();
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extern template int register_conv_params<2>();
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extern template int register_conv_params<3>();
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template <int kSpatialDim>
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c10::intrusive_ptr<ConvPackedParamsBase<kSpatialDim>> PackedConvWeightCudnn<
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kSpatialDim>::
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@ -1,13 +1,5 @@
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#include <torch/library.h>
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int register_linear_params();
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template <int kSpatialDim = 2>
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int register_conv_params();
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extern template int register_conv_params<2>();
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extern template int register_conv_params<3>();
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int register_embedding_params();
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#include <aten/src/ATen/native/quantized/cpu/fbgemm_utils.h>
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TORCH_LIBRARY(quantized, m) {
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m.set_python_module("caffe2.torch.fb.model_transform.splitting.split_dispatcher");
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@ -28,13 +28,6 @@ and /cudnn/ConvUnpackImpl.cpp, for cudnn.
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#include <ATen/ops/from_blob.h>
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#endif
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template <int kSpatialDim = 2>
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int register_conv_params();
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extern template int register_conv_params<2>();
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extern template int register_conv_params<3>();
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namespace at::native {
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namespace {
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@ -13,9 +13,6 @@ and /cudnn/linear_unpack_impl.cpp, for cudnn.
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#include <torch/custom_class.h>
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#include <torch/library.h>
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int register_linear_params();
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namespace at::native {
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namespace {
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@ -96,7 +96,7 @@ static std::shared_ptr<::gloo::transport::Device> makeTCPTLSDevice(
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attr, pkey, cert, caFile, caPath);
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}
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C10_REGISTER_CREATOR(GlooDeviceRegistry, TCP_TLS, makeTCPTLSDevice);
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C10_REGISTER_CREATOR(GlooDeviceRegistry, TCP_TLS, makeTCPTLSDevice)
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#endif
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#if GLOO_HAVE_TRANSPORT_UV
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@ -120,9 +120,9 @@ static std::shared_ptr<::gloo::transport::Device> makeUVDevice(
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// Registry priority is per key identifier. We register UV to `APPLE` for
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// the flexibility of other application to override by priority. Register
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// UV to `UV` for env "GLOO_DEVICE_TRANSPORT" override.
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C10_REGISTER_CREATOR(GlooDeviceRegistry, APPLE, makeUVDevice);
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C10_REGISTER_CREATOR(GlooDeviceRegistry, WIN32, makeUVDevice);
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C10_REGISTER_CREATOR(GlooDeviceRegistry, UV, makeUVDevice);
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C10_REGISTER_CREATOR(GlooDeviceRegistry, APPLE, makeUVDevice)
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C10_REGISTER_CREATOR(GlooDeviceRegistry, WIN32, makeUVDevice)
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C10_REGISTER_CREATOR(GlooDeviceRegistry, UV, makeUVDevice)
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#endif
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namespace {
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@ -153,11 +153,11 @@ void makeStreamsWaitOnOthers(
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C10_DEFINE_REGISTRY_WITHOUT_WARNING(
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TensorPipeTransportRegistry,
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TransportRegistration);
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TransportRegistration)
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C10_DEFINE_REGISTRY_WITHOUT_WARNING(
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TensorPipeChannelRegistry,
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ChannelRegistration);
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ChannelRegistration)
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const std::string& TensorPipeAgent::guessAddress() {
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static const std::string uvAddress = []() {
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@ -284,7 +284,7 @@ std::unique_ptr<ChannelRegistration> makeMultiplexedUvChannel() {
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C10_REGISTER_CREATOR(
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TensorPipeChannelRegistry,
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mpt_uv,
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makeMultiplexedUvChannel);
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makeMultiplexedUvChannel)
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} // namespace
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@ -24,7 +24,7 @@ std::unique_ptr<ChannelRegistration> makeCudaIpcChannel() {
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}
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// The cuda_ipc channels use cudaMemcpy to transmit CUDA tensor across processes
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_ipc, makeCudaIpcChannel);
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_ipc, makeCudaIpcChannel)
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#endif
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@ -44,7 +44,7 @@ std::unique_ptr<ChannelRegistration> makeCudaGdrChannel() {
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// in order to ensure readiness and to agree on the device indices and thus the
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// queue pair to use. It automatically pairs each GPU to the "closest" NIC if
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// there are multiple of them (closest = longest prefix match in PCI tree).
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_gdr, makeCudaGdrChannel);
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_gdr, makeCudaGdrChannel)
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#endif
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@ -55,7 +55,7 @@ std::unique_ptr<ChannelRegistration> makeCudaXthChannel() {
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}
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// The cuda_xth channel supports same-process GPU-to-GPU comm
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_xth, makeCudaXthChannel);
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C10_REGISTER_CREATOR(TensorPipeChannelRegistry, cuda_xth, makeCudaXthChannel)
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std::unique_ptr<ChannelRegistration> makeCudaBasicChannel() {
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auto context = tensorpipe::channel::cuda_basic::create(
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@ -68,7 +68,7 @@ std::unique_ptr<ChannelRegistration> makeCudaBasicChannel() {
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C10_REGISTER_CREATOR(
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TensorPipeChannelRegistry,
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cuda_basic,
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makeCudaBasicChannel);
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makeCudaBasicChannel)
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class TensorpipeCudaConverter : public TensorpipeDeviceTypeConverter {
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public:
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@ -2,15 +2,10 @@
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#include <c10/macros/Macros.h>
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C10_DIAGNOSTIC_PUSH_AND_IGNORED_IF_DEFINED("-Wsuggest-override")
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C10_DIAGNOSTIC_PUSH_AND_IGNORED_IF_DEFINED("-Wnewline-eof")
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#include <onnx/shape_inference/implementation.h>
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C10_DIAGNOSTIC_POP()
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C10_DIAGNOSTIC_POP()
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#include <torch/csrc/jit/ir/ir.h>
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#include <torch/csrc/jit/serialization/export.h>
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#include <mutex>
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#include <unordered_map>
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namespace torch::jit {
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@ -19,18 +19,14 @@
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#include <torch/csrc/onnx/back_compat.h>
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#include <torch/csrc/onnx/onnx.h>
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#include <torch/version.h>
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#include <optional>
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C10_DIAGNOSTIC_PUSH_AND_IGNORED_IF_DEFINED("-Wnewline-eof")
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#include <onnx/checker.h>
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C10_DIAGNOSTIC_POP()
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#include <onnx/onnx_pb.h>
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#include <onnx/proto_utils.h>
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C10_DIAGNOSTIC_PUSH_AND_IGNORED_IF_DEFINED("-Wsuggest-override")
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#include <onnx/shape_inference/implementation.h>
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C10_DIAGNOSTIC_POP()
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#include <memory>
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#include <optional>
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#include <regex>
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#include <set>
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#include <sstream>
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