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doc: update build options page and jit inspection example

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This commit is contained in:
Maria Zhukova
2025-05-06 17:52:03 -07:00
parent 9703c30657
commit 2de3f20043
2 changed files with 8 additions and 7 deletions
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6
doc/build/build_options.md vendored
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@ -116,9 +116,9 @@ Example that enables SSE41 and AVX2 sets:
#### ONEDNN_ENABLE_PRIMITIVE_GPU_ISA
This option supports several values: `ALL` (the default) which enables all
ISA implementations or any set of `GEN9`, `GEN11`, `XELP`, `XEHP`, `XEHPG`,
`XEHPC`, `XE2`, and `XE3`. Selected ISA will enable correspondent parts in
just-in-time kernel generation based implementations. OpenCL based kernels and
ISA implementations or any set of `XELP`, `XEHP`, `XEHPG`, `XEHPC`, `XE2`,
and `XE3`. Selected ISA will enable correspondent parts in just-in-time
kernel generation based implementations. OpenCL based kernels and
implementations will always be available. Example that enables XeLP and XeHP
set:
```

9
doc/performance_considerations/inspecting_jit.md
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@ -41,14 +41,15 @@ Use any disassembler to view the code. For example:
## Example (GPU)
~~~sh
$ ONEDNN_JIT_DUMP=1 ./simple-net-cpp gpu
$ ONEDNN_JIT_DUMP=1 ./cnn-training-f32-cpp gpu
~~~
This will produce the following output files if running on Intel Processor Graphics Gen9:
This will produce the following output files if running on Intel Arc B-series graphics:
~~~sh
dnnl_dump_gpu_simple_reorder.0.bin
dnnl_dump_gpu_gen9_conv_fwd.1.bin
dnnl_dump_gpu_gen_reorder.0.bin
dnnl_dump_gpu_gen_reorder.1.bin
dnnl_dump_gpu_gen_conv.2.bin
...
~~~